Getting Started with VHDL and your FPGA
Start by opening the ISE you downloaded from the Xilinx website. Click 'File' then 'New Project' and a box should pop up. First you will need to title your project, we named it "Led_Control" (you can not have spaces in the project names, use underscore instead). Next you will have to input the device specifics, it will remember these values for future projects. Under 'family' and 'device' find the corresponding FPGA you will be using and select it. Under preferred language select VHDL, then press next. You can either add a new source on the next page or make it later, for simplicity we will add it now, click 'New Source' then select 'VHDL Module' and give it a name. Next it will ask to create the ports, you will need two. The first will be 'BTNS', 'in' and it will have a bus of 8. The second will be 'LEDS', 'out' and will also have a bus of 8. Once you are done click next and then finish. You should have a fresh new module in front of you.
So how do we make these LED's light up? We can do this a number of ways, in this case we will be assigning them to corresponding buttons, an alternative would be to assign them a value of '1'. We write the operation after the line 'begin' and the line 'end'. Begin by typing "LEDS(0) <= BTNS(0);" This will assign the LED to the corresponding switch. The numbers simply indicate which LED in the bus you are referring too. Once you have done this for all 8 LED's, it is time to make a contraint file. On the left side of the ISE should be a box, go to the 'Design' tab and then find at the top of the box where it has your file "Led_Control" and right click on the file. Select 'New Source' and this time choose the 'Implementation Constraints file', this should open a new module where you will assign the physical outputs and inputs on the board with those used in the program. Refer to your reference manual to find these values, the ones provided will only work on the NEXYS board.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Led_Control is Port ( BTNS : in STD_LOGIC_VECTOR(7 downto 0); LEDS : out STD_LOGIC_VECTOR(7 downto 0) ); end Led_Control; architecture Behavioral of Led_Control is begin LEDS(0) <= BTNS(0); LEDS(1) <= BTNS(1); LEDS(2) <= BTNS(2); LEDS(3) <= BTNS(3); LEDS(4) <= BTNS(4); LEDS(5) <= BTNS(5); LEDS(6) <= BTNS(6); LEDS(7) <= BTNS(7); end Behavioral;
Contraints File: The values after "LOC" are found in the reference manual for your device.
NET "LEDS<0>" LOC="L14"; NET "LEDS<1>" LOC="L13"; NET "LEDS<2>" LOC="M14"; NET "LEDS<3>" LOC="L12"; NET "LEDS<4>" LOC="N14"; NET "LEDS<5>" LOC="M13"; NET "LEDS<6>" LOC="P14"; NET "LEDS<7>" LOC="R16"; NET "BTNS<0>" LOC="N15"; NET "BTNS<1>" LOC="J16"; NET "BTNS<2>" LOC="K16"; NET "BTNS<3>" LOC="K15"; NET "BTNS<4>" LOC="L15"; NET "BTNS<5>" LOC="M16"; NET "BTNS<6>" LOC="M15"; NET "BTNS<7>" LOC="N16";
After assigning all of the values go back to the main module, here you will click 'Synthesize" on the lower left box and the click "Check Syntax". If it is successfull double click "Generate Programming File" underneath it, if it fails to check syntax or create a file, find the error in the console at the bottom of the ISE and fix the problem and try again. Once it successfully generates the programming file connect your FPGA to the computer with the USB cable and turn it on. Open up the Adept 2.0 program you downloaded from Xilinx and find your device. There should be two places you can upload the program too, the flash memory and the FPGA, the flash memory will remember the program even after turning it off however the FPGA will not. Go ahead and just load it onto the FPGA and test it out. If you upload it to the Flash you will need to hit the reset button on the board after it uploads, this will erase previous memory and execute the new code.
Have fun playing with those LED's. There are many sample programs and tutorials out there for VHDL, we suggest you find a few and learn how to use clocks and program 7 segment displays.