Errrggghhh.... Problem - Interrupts - SREG

[TrickyNekro]

Hello again...
I'm having a problem and I really don't know what going on... it seems I miss something badly...

At the SREG the I-bit must be set for interrupts to recognized and readdressed...
Although external interrupts happen... if I set this bit...
Timer interrupts don't work!!! That's frustrating...
I think there is a another register that I must tinker but
I don't know the name and I'm a little bit lost!!!
Saving registers doesn't work either... But if it was for registers then external interrupts should have problem too!!!
Aaagghhh... Darn assembly... but it's becoming useful!!!


Thanks in advance,
Lefteris, Greece

[pomprocker]

What processor?

[TrickyNekro]

ATMEGA32 sorry

[pomprocker]

TIFR, TIMSK, GIFR, GICR

Read the datasheet regarding these registers

[TrickyNekro]

These all are set good to go!!!

The problem is this... my compiler has the command enable interrupts...
Enabling global interrupts is setting the SREG = 128
If I type the command ENABLE INTERRUPTS then everything ok
Both external and internal are set... No matter how I configure the registers...
But if I write SREG = 128 (= &B10000000 )
Then the microcontroller responds only to external interrupts!!!

Since my compiler (BASCOM-AVR) helps me learn and explore the hardware plus being able to write in
Assembler, I don't want to just type the command, but to tinker the register a little...
I lean to learning Assembler... And BASCOM only makes it easier...

I really don't know what to do here...
I heard somewhere about a register starting from E.... 
And that you need to set it properly in order for internal interrupts to happen....
I'm little confused... that's for sure....


Thanks for the reply and thanks in advance!!!!
Lefteris,
Greece

[pomprocker]

On page 13 of your datasheet

Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate reset
vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 256 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more
information. The Reset Vector can also be moved to the start of the boot Flash section by pro-
gramming the BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-
Programming” on page 244.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction


The answers are in your datasheet man keep looking!

[TrickyNekro]

Ok thanks for the help pal!!!

I corrected the problem.... But.... I have a question more....

If I-bit is the seventh bit of the SREG....
Why when I write SREG = &B10000000 it doesn't work....
I issued a SEI command to do the trick....

Darn Assembly is a hell of useful tool....

And thanks again!!!!

Best Regards,
Lefteris, Greece