Author Topic: FPGA I/O lines  (Read 2978 times)

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Offline AdminTopic starter

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FPGA I/O lines
« on: February 26, 2007, 10:05:07 AM »
Does anyone know more about the I/O lines of a FPGA?

The problem Ive always had with microcontrollers is not enough I/O lines. I often need 20+ digital and 15+ ADC. I hear that these FPGA's often have a hundred+ pins and Im curious about the functionality of these things . . .

If I can find one small enough, I might make an investment. Plus, they are probably the future in robotics, so I should make an investment . . .

Anyone actually own/used one with a strong opinion on what I should look for when buying one?

I might actually be able to get it gov't funded, if it has what my robot fish needs . . .

Offline sdk32285

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Re: FPGA I/O lines
« Reply #1 on: February 26, 2007, 10:44:54 AM »
I'm using a Xilinx Spartan FPGA. It has 200+ I/O lines. When you Synthesize your design to the chip you need to create a user definition file that tells the programmer which signal coresponds to which I/O port and whether its in/out/bi.
Also I have only used Xilinx FPGA'a and their free development studio but I would definitely recommend them.
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Re: FPGA I/O lines
« Reply #2 on: February 26, 2007, 10:57:31 AM »
http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3_fpgas/overview.htm#s3table

What is the difference between 'I/O Standards,' 'Max Differential I/O Pairs,' and 'Max Single Ended I/O'?

Which ones can be used as ADC?

Looking at the prices, they seem to be very affordable (~$68). Xilinx has like 40 different types of FPGAs . . . will take awhile to figure out what I want . . .

What kind of programmer board would I need? What would be the best way you would recommend a beginner to learn how to use a FPGA? How much source code and examples do they offer to start with?

Offline sdk32285

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Re: FPGA I/O lines
« Reply #3 on: February 27, 2007, 02:27:30 PM »
I'm not sure about the different I/O types.
While Programming them i have never needed to worry about that.
The best way to learn about FPGA is to Download the XILINX ISE studio. In this you can do schematic capture or write your own VHDL and then simulate the results (the simulate takes a little time to get used to in order to set you test signals correctly). If you want I can post some simple VHDL code later.
When learning FPGA's the easyest is to look at a preexisting code so you can get quick reminders about signals vs variables and their different formats. Other things such as I/O, type, size, and header info can be done with the wizard or copied and modified easily from preexisting code.

A quick google search gave me http://www.easyfpga.com/ez2susb_features.htm which has reasonably priced devel boards. The only problem is there is no restore EEPROM so it will need to be reprogrammed on every start up.

If your designs are relatively small there are Good CPLD devel boards that are nonvolatile.
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Offline pomprocker

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Re: FPGA I/O lines
« Reply #4 on: November 12, 2008, 12:48:00 AM »
FPGAs loose their functionality when the power goes away (like RAM in a computer that looses its content). You have to re-download them when power goes back up to restore the functionality.

FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...).



Here is from wikipedia:

FPGAs are usually programmed after being soldered down to the circuit board, in a manner similar to that of larger CPLDs. In most larger FPGAs the configuration is volatile, and must be re-loaded into the device whenever power is applied or different functionality is required. Configuration is typically stored in a configuration PROM or EEPROM. EEPROM versions may be in-system programmable (typically via JTAG).

The main difference between FPGAs and CPLDs is that FPGAs have a volatile memory, thus it requires to be programmed after power up. CPLDs do not. Also, FPGAs usually consume more power than CPLDs due to their SRAM nature. Finally, CPLDs do not have as many registers or memory storage as FPGAs. In general CPLDs are a good choice for wide combinatorial logic applications while FPGAs are more suitable for large state machines (i.e. microprocessors).
« Last Edit: November 12, 2008, 11:21:50 AM by pomprocker »

 


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