Possible race condition prevention?

[macdad-]

Hello everyone,

I've finished designing the schematics for my next robot and a Logic Chip Computer Project. Both of which use 74HC/74AC CMOS logic chips. I noticed several potential flaws in the motor controller input in my robot as it's inputs are shared by two seperate logic circuits which could lead to unneccesary/damaging sinking/sourcing of outputs. I put in signal diodes(1N4148 Silicon) on their outputs to prevent this and added pull-downs to the inputs of the motor controller just in case. I am still hesitant, could someone confirm that the diodes and pull-ups will prevent a race condition/output sharing scenario.

Thanks

[Soeren]

The schematic is very hard to read

[macdad-]

Sorry, here it is. It's just a sample of the full circuit(I have yet to draw it in ExpressSCH, I'm just drawing it on paper  ). SW1 is the Mode switch of entire robot that switches it from Line Following mode to Exploration mode which each Mode's logic output are controlled via the AND gates in the schematic. IXDN404PI is not a motor controller, but I'm using it as such. It works like a buffer/driver. I've added in D1 and D2, the two signal diodes to protect against race condition/back-sourcing to the other gate. R4 and R5 are the pull-downs to further protect against R.C.

The AND gates of each mode's logic circuits are sharing outputs to the IXDN404PI's input. Will this be enough to prevent race condition?

[Graynomad]

As that circuit stands I don't see how you can get a race condition, there is the potential for some confusion when you flick the switch which may or may not be a problem for this specific application. From what I can see of the IXDN404PI it just takes a logic input and turns one or other of the FETs on. You can't stuff that up regardless of what happens with the AND gates.

You might get some switch bounce that would cause fast switching of the motor, I doubt that would matter because it wouldn't be able to respond fast enough.

Frankly I doubt you need the gates, just use a SPDT switch, as long as the AND inputs are logic levels that's effectively the same thing.

However if this is half of a bridge that may be a different story.

Also R1 should go, it does nothing but form a voltage divider that will confuse the AND gates 

______
Rob

[macdad-]

As that circuit stands I don't see how you can get a race condition, there is the potential for some confusion when you flick the switch which may or may not be a problem for this specific application. From what I can see of the IXDN404PI it just takes a logic input and turns one or other of the FETs on. You can't stuff that up regardless of what happens with the AND gates.

You might get some switch bounce that would cause fast switching of the motor, I doubt that would matter because it wouldn't be able to respond fast enough.

Frankly I doubt you need the gates, just use a SPDT switch, as long as the AND inputs are logic levels that's effectively the same thing.

Thanks,

Yes, the mode switch is a SPDT slide switch, so contact bounce shouldn't be a problem I was just worried about the output sharing as when the mode switch is set to one AND gate, regardless of the other AND gate's output, that if it goes HIGH that it'll source over to the other AND gate instead of sourcing to the IXDN404PI. So, sorry if I stated it wrong, but will the diodes prevent the sourcing between gate outputs and only source into the IXDN404PI?

But the AND gates I added in were for controlling which logic circuit(Exploration vs Line Following) had control for the motors.

,Nick(macdad-)

[Graynomad]

it goes HIGH that it'll source over to the other AND gate

If the second AND OP was low that would be effectively a dead short to GND which is not good.

but will the diodes prevent the sourcing between gate outputs and only source into the IXDN404PI?

Yep.

______
Rob

[macdad-]

Ok thanks 

[Soeren]

Hi,

I've added in D1 and D2, the two signal diodes to protect against race condition/back-sourcing to the other gate. R4 and R5 are the pull-downs to further protect against R.C.

The AND gates of each mode's logic circuits are sharing outputs to the IXDN404PI's input. Will this be enough to prevent race condition?

There's absolutely no chance of race hazard in this circuit! (Not sure if you really know what race is though - you may have a different interpretation/understanding).
Diode isolated outputs are much older than the 74AC chips you use. What you have made is called a diode-OR gate, no problem there.
As Graynomad mentioned, you need to loose R1. As a rule of thumb, in logic you either use pull-ups or pull-downs, not both at the same time.

For a more readable schematic, try to keep ground (and negative supply) at the bottom and move R4 parallel to R5 so that the more negative end of it is pointing down - not an absolute necessity, but helps others (and yourself some time from now) reading it and it's considered good practice.

[macdad-]

Thanks Soeren.

R1 is there at the mode switch to limit current through the switch, and R2/3 are just for pull-downs in the case that the mode switch is not switched to that corresponding gate.

I could just remove R1 and add two resistors to each of the AND gates' inputs to limit current, and still keep R2/3 as the gate pull-downs.

Race condition, from what I learned was the racing of two signals between gates, in which one signal might get to the gate first before the other due to gate delays. I guess I label the thread wrong. 

And yea, this schematic was thrown together at the last minute. 

[Graynomad]

limit current through the switch

R2/3 will do that, R1 will create a voltage divider that creates a voltage on the gates at some point between 0 and 5v which is not advisable.

add two resistors to each of the AND gates' inputs to limit current

You don't need to limit current to a logic input, it will only draw 5/8ths of 2/5ths of a fempto amp anyway. If you're worried about ESD, over voltage etc that's a different story.

[macdad-]

limit current through the switch

R2/3 will do that, R1 will create a voltage divider that creates a voltage on the gates at some point between 0 and 5v which is not advisable.

add two resistors to each of the AND gates' inputs to limit current

You don't need to limit current to a logic input, it will only draw 5/8ths of 2/5ths of a fempto amp anyway. If you're worried about ESD, over voltage etc that's a different story.

Thanks, I'm still prototyping, but thanks for the heads up.